The present invention generally relates to a method for bumping and backlapping a semiconductor wafer and more particularly, relates to a method for backlapping a semiconductor wafer that has solder bumps formed on an active surface without damaging the bumps in a backlapping process.
In the fabrication of modern semiconductor devices, the ever increasing device density and decreasing device dimensions demand more stringent requirements in the packaging or interconnecting techniques in such high density devices. Conventionally, a flip-chip attachment method has been used in packaging of semiconductor chips. In the flip-chip attachment method, instead of attaching a semiconductor die to a lead frame in a package, an array of solder bumps is formed on the surface of the die. The formation of the solder bumps may be carried out in an evaporation method by using a composite material of tin and lead through a mask for producing a desired pattern of solder bumps. The technique of electrodeposition has been more recently developed to produce solder bumps in flip-chip packaging process.
Other techniques that are capable of solder-bumping a variety of substrates to form solder balls have also been proposed. The techniques generally work well in bumping semiconductor substrates that contain solder structures over a minimal size. For instance, one of such widely used techniques is a solder paste screening method which has been used to cover the entire area of an eight inch wafer. However, with recent trend in the miniaturization of device dimensions and the necessary reduction in bump-to-bump spacing (or pitch), the use of the solder paste screening technique has become more difficult.
Other techniques for forming solder bumps such as the controlled collapse chip connection (C4) technique and the thin film electrodeposition technique have also been used in recent years in the semiconductor fabrication industry. The C4 technique is generally limited by the resolution achievable by a molybdenum mask which is necessary for the process. Fine-pitched solder bumps are therefore difficult to be fabricated by the C4 technique. Similarly, thin film electrodeposition techniques require a ball limiting metallurgy layer to be deposited and defined by an etching process which has the same limitations as the C4 technique. For instance, a conventional thin film electrodeposition process for depositing solder bumps is shown in FIGS. 1Axcx9c1F.
A conventional semiconductor structure 10 is shown in FIG. 1A. The semiconductor structure 10 is built on a silicon substrate 12 with active devices built therein. A bond pad 14 is formed on a top surface 16 of the substrate 12 for making electrical connections to the outside circuits. The bond pad 14 is normally formed of a conductive metal such as aluminum. The bond pad 14 is passivated by a final passivation layer 20 with a window 22 opened by a photolithography process to allow electrical connection to be made to the bond pad 14. The passivation layer 20 may be formed of any one of various insulating materials such as oxide, nitride or organic materials. The passivation layer 20 is applied on top of the semiconductor device 10 to provide both planarization and physical protection of the circuits formed on the device 10.
Onto the top surface 24 of the passivation layer 20 and the exposed top surface 18 of the bond pad 14, is then deposited an under bump metallurgy layer 26. This is shown in FIG. 1B. The under bump metallurgy (UBM) layer 26 normally consists of an adhesion/diffusion barrier layer 30 and a wetting layer 28. The adhesion/diffusion barrier layer 30 may be formed of Ti, TiN or other metal such as Cr. The wetting layer 28 is normally formed of a Cu layer or a Ni layer. The UBM layer 26 improves bonding between a solder ball to be formed and the top surface 18 of the bond pad 14.
In the next step of the process, as shown in FIG. 1C, a photoresist layer 34 is deposited on top of the UBM layer 26 and then patterned to define a window opening 38 for the solder ball to be subsequently formed. In the following electrodeposition process, a solder ball 40 is electrodeposited into the window opening 38 forming a structure protruded from the top surface 42 of the photoresist layer 34. The use of the photoresist layer 34 must be carefully controlled such that its thickness is in the range between about 30 xcexcm and about 40 xcexcm, preferably at a thickness of about 35 xcexcm. The reason for the tight control on the thickness of the photoresist layer 34 is that, for achieving a fine-pitched solder bump formation, a photoresist layer of a reasonably small thickness must be used to achieve a high imaging resolution. It is known that, during a photolithography process, the thicker the photoresist layer, the poorer is the imaging process. To maintain a reasonable accuracy in the imaging process on the photoresist layer 34, a reasonably thin photoresist layer 34 must be used which results in a mushroom configuration of the solder bump 40 deposited therein. The mushroom configuration of the solder bump 40 contributes greatly to the inability of a conventional process in producing fine-pitched solder bumps.
Referring now to FIG. 1E, wherein the conventional semiconductor structure 10 is shown with the photoresist layer 34 removed in a wet stripping process. The mushroom-shaped solder bump 40 remains while the under bump metallurgy layer 26 is also intact. In the next step of the process, as shown in FIG. 1F, the UBM layer 26 is etched away by using the solder bump 40 as a mask in an wet etching process. The solder bump 40 is then heated in a reflow process to form solder ball 42. The reflow process is conducted at a temperature that is at least the reflow temperature of the solder material.
After the solder balls are formed on the wafer surface for the flip chips, the wafer must be thinned in a backlapping process similar to that used in a non-flip chip device. The removal of the backside, or the inactive side, of the wafer is necessary not only to planarize the wafer backside, but also to reduce the thickness dimension of the IC chip fabricated.
A conventional backlapping process used for thinning a flip chip packaged wafer is shown in FIGS. 2Axcx9c2C. The backlapping process is conducted on semiconductor wafers in order to correct any curvature in the wafer and to achieve planarity and parallelism of the top and bottom surfaces of a wafer. Since a wafer polishing process can only remove a maximum thickness of about 5 xcexcm, the polishing process cannot be used effectively to correct the curvature of the wafer and to achieve parallelism of the surfaces. The lapping, or backlapping process, is used before a wafer polishing process to achieve the major thickness reduction. The wafer lapping process can be carried out in a lapping apparatus which may be a single-side lapping or a double-side lapping.
When a conventional backlapping process is utilized in lapping the backside of a flip chip packaged wafer, as shown by structure 10 of FIG. 2A, numerous processing difficulties have been discovered. The conventional backlapping process requires the mounting of a protective tape 44 to the top of the active surface of the wafer, i.e. to the top of the solder balls 42, as shown in FIG. 2B. However, instead of a relatively planar top surface formed by bond pads covered by a passivation layer on a non-flip chip wafer, the protective tape 44 which is adhesively bonded to the top of the solder balls 42 does not adequately protect the solder balls 42 during a backlapping process. For instance, as shown in FIG. 2C, due to the high pressure necessary for mounting the protective tape 44 and the high pressure applied during lapping, even though the thickness of the substrate 12 is significantly reduced to a thickness 46, the solder balls 42 can fall off or be crushed during the lapping process.
A process flow chart for the conventional backlapping process that utilizes a protective tape is shown in FIG. 3. It is noted that in the conventional backlapping process 50, the UBM sputtering step 52, the dry film resist lamination step 54, the photoresist exposure/developing step 56, the solder electroplating step 58, the resist stripping step 60 and the solder reflow step 62 are substantially similar to that shown in FIGS. 1Bxcx9c1F. The protective tape mounting step 64, the backside lapping step 66 and the demounting of the protective tape step 68 are substantially shown in FIGS. 2Axcx9c2C.
It is therefore an object of the present invention to provide a method for bumping and backlapping a semiconductor wafer that does not have the drawbacks or shortcomings of the conventional method when a protective tape is utilized.
It is another object of the present invention to provide a method for bumping and backlapping a semiconductor wafer without causing damages to the solder balls formed on the flip chip package.
It is a further object of the present invention to provide a method for bumping and backlapping a semiconductor wafer prior to a solder reflow process and prior to the formation of solder balls.
It is another further object of the present invention to provide a method for bumping and backlapping a semiconductor wafer wherein the backlapping process is conducted while solder bumps are protected by a photoresist layer.
It is still another object of the present invention to provide a method for bumping and backlapping a semiconductor wafer by mounting a protective tape on top of a dry film photoresist layer for protecting the solder bumps.
It is yet another object of the present invention to provide a method for bumping and backlapping a semiconductor wafer wherein a wafer backside thickness can be reduced by at least 40% of its original thickness without damaging the solder bumps.
It is still another further object of the present invention to provide a method for bumping and backlapping a semiconductor wafer wherein a backside of a wafer is first lapped before the solder bumps are reflown into solder balls.
In accordance with the present invention, a method for bumping and backlapping a semiconductor wafer that has flip chip packages formed on top without damaging the solder balls is provided.
In a preferred embodiment, a method for bumping and backlapping a semiconductor wafer can be carried out by the steps of first providing a pre-processed wafer that has a multiplicity of bond pads on a top surface; depositing a under-bump-metallurgy layer on the top surface of the wafer; laminating a dry film resist layer on top of the UBM layer; patterning the dry film resist layer with a multiplicity of openings exposing the multiplicity of bond pads; depositing a solder into the multiplicity of openings forming a multiplicity of solder bumps; mounting a protective tape on top of the dry film resist layer; and removing a preselected thickness from a bottom surface of the wafer.
The method for bumping and backlapping a semiconductor wafer may further include the step of reflowing the multiplicity of solder bumps to a multiplicity of solder balls after the removing step, or the step of mounting the protective tape on top of the dry film resist layer by adhesive means, or the step of providing the protective tape with an adhesive layer coated on one side. The method may further include the step of mounting the wafer in a backlapping apparatus with the protective tape facing downwardly and the bottom surface of the wafer exposed. The method may further include the step of removing at least 40% of the thickness of the wafer from the bottom surface of the wafer, or the step of stripping the protective tape and the dry film resist layer sequentially from the top surface of the wafer after the removing step. The method may further include the step of providing the protective tape in an insulating material, or the step of depositing solder into the multiplicity of openings by an electroplating technique or by a stencil printing technique.
The present invention is further directed to a method for backlapping a semiconductor wafer that has a multiplicity of solder bumps formed on an active surface which can be carried out by the operating steps of first providing a semiconductor wafer that has a multiplicity of solder bumps formed in a dry film photoresist layer; mounting a protective film to a top surface of the dry film photoresist layer with an inactive surface of the wafer exposed; and removing a preselected thickness from the inactive surface of the wafer in a lapping process.
The method for backlapping a semiconductor wafer that has a multiplicity of solder bumps formed on an active surface may further include the step of patterning the dry film photoresist layer with a multiplicity of openings exposing a multiplicity of bond pads prior to a solder filling step for forming the multiplicity of solder bumps, or the step of stripping the protective film from the top surface of the dry film photoresist layer after the removing step, or the step of stripping the protective film and the dry film resist layer sequentially from the active surface of the wafer.
The method for backlapping a semiconductor wafer may further include the step of removing at least 40% of the thickness of the wafer from the inactive surface of the wafer during the removing step, or the step of reflowing the multiplicity of solder bumps into a multiplicity of solder balls after the stripping step, or the step of removing a preselected thickness from the inactive surface of the wafer such that a final thickness of not more than 300 xcexcm is obtained when the wafer is a 300 mm diameter wafer. The method may further include the step of removing the preselected thickness from the inactive surface of the wafer in a lapping process by utilizing a slurry solution.